Semiconductor element and manufacturing method thereof

ABSTRACT

A p-channel MOSFET ( 1 ) includes a semiconductor substrate ( 2 ), an epitaxial region ( 3 ), a second diffusion region ( 6 ), and a drain region. The epitaxial region ( 3 ) is formed on the upper surface of the semiconductor substrate ( 2 ). The second diffusion region ( 6 ) is formed in a predetermined upper surface area of the epitaxial region ( 3 ). The second diffusion region ( 6 ) has a central portion ( 6   a ) and a peripheral portion ( 6   b ). The central portion ( 6   a ) is formed substantially at the center of the epitaxial region ( 3 ) and formed thicker than the peripheral portion ( 6   b ). The peripheral portion ( 6   b ) is formed in an annular shape so as to surround the central portion ( 6   a ). The drain region ( 7 ) is formed in an upper surface area of the central portion ( 6   a ) of the second diffusion region ( 6 ).

This application is a 371 of PCT/JP03/05334, filed Apr. 25, 2003.

1. Technical Field

The present invention relates to a semiconductor element, andparticularly relates to a semiconductor element having a structurecalled RESURF structure and a manufacturing method thereof.

2. Background Art

As a semiconductor element mounted on an Integrated Circuit, there is ap-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor)having a structure called RESURF structure. FIG. 3 shows one example ofthis kind of p-channel MOSFET.

A p-channel MOSFET 101 (hereinafter referred to as MOSFET 101) comprisesa p⁻ type semiconductor substrate 102, an n⁻ type epitaxial region 103formed on the upper surface of the semiconductor substrate 102 by anepitaxial growth method or the like, and p⁺ type isolation regions 104for isolating each MOSFET 101 to be mounted on an integrated circuit, byutilizing a reverse bias of p-n junction.

Further, the MOSFET 101 comprises p⁻ type diffusion regions 105 formedin an upper surface area of the epitaxial region 103, and p⁺ type drainregions 106 formed in the upper surface area of the epitaxial region 103so as to contact the diffusion regions 105.

Furthermore, the MOSFET 101 comprises, when it is seencross-sectionally, p⁺ type source regions 107 formed in the surface areaof the epitaxial region 103 between the diffusion regions 105, and an n⁺type back gate region 108 formed in the surface area of the epitaxialregion 103 so as to be sandwiched by the source regions 107.

Gate insulation films 109 are formed on the upper surface of theepitaxial region 103 between the diffusion region 105 and the sourceregion 107. Gate electrodes 110 are formed on the gate insulation films109. Of the surface area of the epitaxial region 103, surface areasfacing the gate electrodes 110 via the gate insulation films 109function as channel regions.

Drain electrodes 111, source electrodes 112, a back gate electrode 113,and ground electrodes 114 to be grounded are formed on the uppersurfaces of the drain regions 106, the upper surfaces of the sourceregions 107, the upper surface of the back gate region 108, and theupper surfaces of the isolation regions 104, respectively. Of the uppersurface of the MOSFET 101, surfaces other than the surfaces on which thegate insulation film 109, the gate electrodes 110, the drain electrodes111, the source electrodes 112, the back gate electrode 113, and theground electrodes 114 are formed are covered with a field oxide film115.

As described above, the MOSFET 101 has a so-called double RESURFstructure in which the n⁻ type epitaxial region 103 is formed on the p⁻type semiconductor substrate 102, and the p⁻ type diffusion regions 105are formed in the surface area of the epitaxial region 103.

The MOSFET 101 having the double RESURF structure has its epitaxialregion 103 and diffusion region 105 substantially depleted, when avoltage of equal to or greater than predetermined value is applied tobetween the source electrode 112 and the drain electrode 111. Due tothis, the potential is fixed and the electric field density per unitarea of the epitaxial region 103 is reduced. As a result, effects suchas improvement in voltage withstandability can be obtained.

The MOSFET 101, which utilizes the high voltage withstandability due tothe (double) RESURF structure, has a variety of uses, and may be used ina level-shift down circuit. In a case where used in a level-shift downcircuit, the MOSFET 101 is required to have a voltage withstandabilitythat is enough to withstand a drain voltage higher by ten plus severalvolts than a voltage of the semiconductor substrate 102. The MOSFET 101having the above-described structure can easily adapt to such a request.

However, in a case where used for a purpose which requires a voltagewithstandability enough to withstand a further higher voltage level, theMOSFET 101 having the above-described structure cannot adapt to asituation where the drain voltage changes from a ground level to ahigher voltage level.

In the MOSFET 101, the isolation regions 104 at a ground level areformed near the drain regions 106 in order to maintain the balance ofelectric charges near the drain regions 106 good. However, with thisstructure, the electric field strength between the drain region 106 andthe isolation region 104 rises in a case where the voltage level of thedrain voltage changes to a higher level in a plus direction with respectto the ground level, and there might be caused a punch through or abreakdown at a voltage level lower than a desired voltage level.

The present invention was made in view of the above circumstance, and anobject of the present invention is to provide a semiconductor elementhaving an excellent high voltage withstandability and a manufacturingmethod thereof.

Another object of the present invention is to provide a semiconductorelement in which a punch through or an undesirable breakdown is noteasily caused, and a manufacturing method thereof.

DISCLOSURE OF INVENTION

To achieve the above objects, a semiconductor element according to afirst aspect of the present invention comprises: a first semiconductorregion (2) of a first conductive type; a second semiconductor region (3)of a second conductive type which is formed on one principal surface ofthe first semiconductor region; a third semiconductor region (6) of afirst conductive type which is formed in a predetermined surface area ofthe second semiconductor region (3); a fourth semiconductor region (7)of a first conductive type which is formed in a surface area of thethird semiconductor region (6) and has a higher impurity concentrationthan the third semiconductor region has; and a fifth semiconductorregion (8) which is formed in a surface area of the second semiconductorregion (3) so as to surround the third semiconductor region (6),wherein: the third semiconductor region (6) has a central portion (6 a)which surrounds the fourth semiconductor region, and a peripheralportion (6 b) which surrounds the central portion (6 a); the centralportion (6 a) is formed to have a depth from a surface of the secondsemiconductor region (3) that is deeper than that of the peripheralportion (6 b); and a part of the second semiconductor region (3)arranged right under the central portion (6 a) has a smaller amount ofelectric charges than an amount of electric charges of a part of thesecond semiconductor region (3) arranged right under the peripheralportion (6 b), because the part of the second semiconductor region (3)arranged right under the central portion (6 a) has a thickness thinnerthan that of the part of the second semiconductor region (3) arrangedright under the peripheral portion (6 b).

In the semiconductor element having such a structure, the firstsemiconductor region, the second semiconductor region, and the fourthsemiconductor region form a RESURF structure. Due to this, electricfield relaxation in the horizontal direction of the semiconductorelement is favorably achieved and effects such as improvement in thevoltage withstandability can be obtained. Further, in the semiconductorelement having such a structure where a part of the second semiconductorregion right under the central portion is formed relatively thin, theamount of electric charges possessed by the part of the secondsemiconductor region right under the central portion is relativelysmall. Due to this, even when a voltage of a ground level is applied tothe fourth semiconductor region, the electric charge balance near thefourth semiconductor region is prevented from being destroyed. Further,a part of the second semiconductor region arranged right under theperipheral portion is formed relatively thick. This thickness providesthe part of the second semiconductor region arranged right under theperipheral portion with a sufficient amount of electric charges forpreventing occurrence of a punch through or the like when a voltage of arelatively high voltage level is applied to the fourth semiconductorregion. Accordingly, the semiconductor element of the present inventioncan adapt to every situation in which the voltage applied to the fourthsemiconductor region changes from the ground level to a higher level,and thus can obtain under every situation, the effect of improving thevoltage withstandability due to the possession of the RESURF structure.

The semiconductor element may further comprise: a drain electrode (12)formed on the fourth semiconductor region (7); a source electrode (13)formed on the fifth semiconductor region (8); a gate insulation film(10) covering the second semiconductor region (3) between the thirdsemiconductor region (6) and the fifth semiconductor region; and a gateelectrode (11) formed on the gate insulation film (10).

The semiconductor element may further comprise: an isolation region (4)of a first conductive type which is formed at an outer edge of thesecond semiconductor region (3); and a sixth semiconductor region (5)which is formed in a surface area of the second semiconductor region (3)so as to contact the isolation region (4), the part of the secondsemiconductor region (3) which is present right under the sixthsemiconductor region (5) may have almost a same thickness as that of thepart of the second semiconductor region (3) which is present right underthe peripheral portion (6 b).

The third semiconductor region (6) may be formed at generally the centerof the surface of the second semiconductor region (3), and the fourthsemiconductor region (7) may be formed at generally the center of thesurface of the third semiconductor region (6).

The semiconductor element may further comprise a ground electrode (15)which is formed on the isolation region (4), and the secondsemiconductor region (3) and the third semiconductor region (6) may besubstantially depleted when a voltage of a predetermined level isapplied to between the gate electrode (10) and the drain electrode (12)and the ground electrode (15) is grounded.

The part of second semiconductor region (3) right under the centralportion (6 a) may have such an amount of electric charges as to maintainan electric charge balance near the fourth semiconductor region (7) in acase where a voltage level of a voltage applied to the fourthsemiconductor region (7) is a ground level, and the part of the secondsemiconductor region (3) right under the peripheral portion (6 b) mayhave such an amount of electric charges as to maintain an electriccharge balance near the fourth semiconductor region (7) in a case wherea voltage level of a voltage applied to the fourth semiconductor region(7) is a high level in a plus direction with respect to the groundlevel.

To achieve the above objects, a manufacturing method of a semiconductorelement according to a second aspect of the present invention comprises:a step of forming a second semiconductor region (3) of a secondconductive type on a semiconductor substrate (2) which constitutes afirst semiconductor region of a first conductive type; a step of formingin a surface area of the second semiconductor region (3), a thirdsemiconductor region (6) of a first conductive type which includes acentral portion (6 a) and a peripheral portion (6 b) having differentdepths from each other, wherein the central portion (6 a) is formed in apredetermined surface area of the second semiconductor region (3), andthe peripheral portion (6 b) is formed in a surface area of the secondsemiconductor region (3) so as to abut on the central portion (6 a) andsurround the central portion (6 a) and to have a depth shallower thanthe depth of the central portion (6 a); and a step of forming a fourthsemiconductor region (7) of a first conductive type having a higherimpurity concentration than the third semiconductor region (6) has, in asurface region of the central portion (6 a) included in the thirdsemiconductor region (6).

In a semiconductor element manufactured by such a manufacturing method,the first semiconductor region, the second semiconductor region, and thefourth semiconductor region form a RESURF structure. Due to this,electric field relaxation in the horizontal direction of thesemiconductor element is favorably achieved, and effects such asimprovement in the voltage withstandability can be obtained. Further,since the central portion is formed deeper than the peripheral portion,the part of the second semiconductor region right under the centralportion is thinner than the part of the second semiconductor regionright under the peripheral portion. Accordingly, the part of the secondsemiconductor region right under the central portion has a relativelysmall amount of electric charges while the part of the secondsemiconductor region right under the peripheral portion has a relativelylarge amount of electric charges. Due to this, this semiconductorelement can prevent the electric charge balance near the fourthsemiconductor region from being destroyed under every situation in whichthe voltage applied to the fourth semiconductor region changes from theground level to a high level. As a result, this semiconductor elementcan obtain under every situation, the effect of improving the voltagewithstandability due to the possession of the RESURF structure.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross sectional view showing a structure of a p-channelMOSFET according to an embodiment of the present invention;

FIG. 2 is a plan view of the p-channel MOSFET of FIG. 1; and

FIG. 3 is a cross sectional view showing one example of a structure of aconventional p-channel MOSFET.

BEST MODE FOR CARRYING OUT THE INVENTION

A semiconductor element according to an embodiment of the presentinvention will now be specifically explained with reference to FIG. 1and FIG. 2, by employing a p-channel MOSFET (Metal Oxide SemiconductorField Effect Transistor) to be mounted on an integrated circuit as anexample.

As shown in FIG. 1, a p-channel MOSFET 1 (hereinafter referred to asMOSFET 1) comprises a semiconductor substrate 2, an epitaxial region 3,an isolation region 4, a first diffusion region 5, a second diffusionregion 6, a drain region 7, a source region 8, and a back gate region 9.Further, the MOSFET 1 comprises a gate insulation film 10, a gateelectrode 11, a drain electrode 12, a source electrode 13, a back gateelectrode 14, a ground electrode 15, and a field insulation film 16.Explanation will be made below with reference to FIG. 1, unless adrawing number is otherwise specified.

The semiconductor substrate 2 is constituted by a first conductive type,for example, a p⁻ type semiconductor substrate.

The epitaxial region 3 is constituted by a second conductive type, forexample, an n⁻ type semiconductor region which is formed on one (upper)principal surface of the semiconductor substrate 2 by an epitaxialgrowth method. The epitaxial region 3 functions as a drain regionthrough which a drain current flows in a horizontal direction of FIG. 1.

The isolation region 4 is constituted by a p⁺ type semiconductor regionwhich is formed by diffusing a p-type impurity into a predeterminedregion of the epitaxial region 3. The isolation region 4 has an annularshape that surrounds the epitaxial region 3. The isolation region 4isolates each MOSFET 1 mounted on an integrated circuit, by utilizing areverse bias of p-n junction.

The first diffusion region 5 is constituted by a p⁻ type semiconductorregion which is formed by diffusing a p-type impurity into the surfacearea of the outer edge of the epitaxial region 3. The first diffusionregion 5 is formed so as to contact the isolation region 4, and isformed so as to extend from the isolation region 4 toward the center ofthe epitaxial region 3, when seen cross-sectionally. As shown in FIG. 2,the first diffusion region 5 has an annular shape that surrounds theouter edge of the epitaxial region 3, when seen from above the MOSFET 1.

In FIG. 2, the gate insulation film 10, the gate electrode 11, the drainelectrode 12, the source electrode 13, the back gate electrode 14, theground electrode 15, and the field insulation film 16 are omitted tomake the structure of the first diffusion region 5, etc. easier tounderstand.

The second diffusion region 6 is constituted by a p⁻ type semiconductorregion which is formed by diffusing a p-type impurity into generally thecenter portion of the surface area of the epitaxial region 3. When seencross-sectionally, the second diffusion region 6 comprises a centralportion 6 a and a peripheral portion 6 b which are different in depth.

The central portion 6 a is formed thicker than the peripheral portion 6b. As shown in FIG. 2, the central portion 6 a is formed at generallythe center portion of the MOSFET 1 when seen from above the MOSFET 1.

The peripheral portion 6 b is formed to have almost the same thicknessas that of the first diffusion region 5. As shown in FIG. 2, theperipheral portion 6 b is formed into an annular shape so as to surroundthe central portion 6 a (or outer edge thereof).

The epitaxial region 3 intervenes between the second diffusion region 6and the semiconductor substrate 2. The epitaxial region 3 is relativelythin right under the central portion 6 a and is relatively thick rightunder the peripheral portion 6 b, due to the difference in thicknessbetween the central region 6 a and the peripheral region 6 b. Thethickness of the epitaxial region 3 present right under the peripheralportion 6 b is almost the same as the thickness of the epitaxial region3 present right under the first diffusion region 5.

The drain region 7 is constituted by a p⁺ type semiconductor regionwhich is formed by diffusing a p-type impurity into the surface area ofthe second diffusion region 6. (central portion 6 a) and which has ahigher p-type impurity concentration than that of the second diffusionregion 6. As shown in FIG. 2, the drain region 7 is formed at almost thecenter of the second diffusion region 6. As shown in FIG. 1, the centralportion 6 a is present right under the drain region 7, and this centralportion 6 a functions as a drain-drift region.

The source region 8 is constituted by a p⁺ type semiconductor regionwhich is formed by diffusing a p-type impurity into the upper surfacearea of the epitaxial region 3. As shown in FIG. 2, the source region 8has an annular shape that surrounds the second diffusion region 6(peripheral portion 6 b) via the epitaxial region 3.

The back gate region 9 is constituted by an n⁺ type semiconductor regionwhich is formed by diffusing an n-type impurity into the surface area ofthe epitaxial region 3 and hose n-type impurity concentration is higherthan the n-type impurity concentration of the epitaxial region 3. Asshown in FIG. 2, the back gate region 9 has an annular shape thatsurrounds the source region 8 via the epitaxial region 3.

The gate insulation film 10 is constituted by a silicon oxide film orthe like. The gate insulation film 10 is formed so as to cover the uppersurface of the epitaxial region 3 that is sandwiched by the seconddiffusion region 6 and the source region 8, and a part of the uppersurface of the source region 8.

The gate electrode 11 is constituted by a conductive film made ofpolysilicon, metal, or the like, and is formed on the gate insulationfilm 10 by CVD (Chemical Vapor Deposition) or the like.

The drain electrode 12, the source electrode 13, the back gate electrode14, and the ground electrode 15 are constituted by a conductive filmmade of metal or the like, and are formed respectively on the drainregion 7, the source region 8, the back gate region 9, and the isolationregion 4 by CVD or the like.

The field insulation film 16 is constituted by, for example, a siliconoxide film. The field insulation film 16 covers, of the upper surface ofthe MOSFET 1, surfaces on which the gate insulation film 10, the gateelectrode 11, the drain electrode 12, the source electrode 13, the backgate electrode 14, and the ground electrode 15 are not formed. The filedinsulation film 16 is formed thicker than the gate insulation film.

In the MOSFET 1 having the above-described configuration, a first RESURFstructure constituted by the p⁻ type first diffusion region 5, the n⁻type epitaxial region 3, and the p⁻ type semiconductor substrate 2 isformed. Further, in the center of the MOSFET 1, a second RESURFstructure constituted by the p⁻ type second diffusion region 6, the n⁻type epitaxial region 3, and the p⁻ type semiconductor substrate 2 isformed. Therefore, the MOSFET 1 has a so-called double RESURF structure.

The epitaxial region 3 in the first RESURF structure and the seconddiffusion region 6 in the second RESURF structure are substantiallydepleted by grounding the ground electrode 15 and applying a voltage ofequal to or greater than a predetermined level to between the gateelectrode 11 and the drain electrode 12. Due to this, the potential isfixed and an electric field in the horizontal direction of FIG. 1 isdesirably relaxed. As a result, effects such as improvement in thevoltage withstandability can be obtained. The effect of improving thevoltage withstandability is also achieved in a single RESURF structure.However, the MOSFET 1 including two RESURF structures is better ineffect of improving the voltage withstandability than a case where itincludes a single RESURF structure.

As explained above, in the MOSFET 1 according to the present embodiment,the central portion 6 a which is formed relatively thicker is arrangedright under the drain region 7. This makes the epitaxial region 3 rightunder the central portion 6 a thinner, and makes the amount of electriccharges possessed by the epitaxial region 3 right under the centralportion 6 a smaller than the amount of electric charges possessed by theepitaxial region 3 right under the peripheral portion 6 b. In aconventional MOSFET, an electric charge balance is established by anelectric field from an isolation region or the like. As compared withthis, in the MOSFET 1 according to the present embodiment, an electriccharge balance is established by an electric filed from the drain region7 or the like by reducing the amount of electric charges.

For example, assume that the thickness of the central portion 6 a isalmost the same as that of the peripheral portion 6 b and the thicknessof the epitaxial region 3 right under the central portion 6 a is almostthe same as the thickness of the epitaxial region 3 right under theperipheral portion 6 b. In this case, when the voltage level of thedrain voltage changes to the ground level and the voltages of the gate,source, and back gate change to plus voltages, the electric chargebalance near the drain region 7 is destroyed and a breakdown is causedat a relatively low drain voltage. However, the MOSFET 1 according tothe present embodiment prevents the electric charge balance near thedrain region 7 from being destroyed, by reducing the amount of electriccharges possessed by the epitaxial region 3 right under the drain region7. Therefore, in the MOSFET 1 according to the present embodiment, abreakdown is not caused at a relatively low voltage.

However, if the amount of electric charges is too small, the electriccharge balance is destroyed when the voltage level of the drain voltagechanges to a higher level in a plus direction with respect to the groundlevel, and a punch through occurs in the p⁻ type semiconductor substrate2 and p⁺ type drain region 7. Hence, in the MOSFET 1 according to thepresent embodiment, the epitaxial region 3 right under the peripheralportion 6 b is made relatively thick by making the peripheral portion 6b thinner than the central portion 6 a, in order for the epitaxialregion 3 to have an amount of electric charges which is sufficient forpreventing occurrence of a punch through.

By keeping the balance of depth and concentration profile between thecentral portion 6 a and the peripheral portion 6 b or the balance ofthickness or the like between the epitaxial region 3 under the centralportion 6 a and the epitaxial region 3 under the peripheral portion 6 b,the MOSFET 1 according to the present embodiment can adapt to asituation in which the voltage level of the drain voltage changes fromthe ground level to a higher level in the plus direction. Therefore, theMOSFET 1 can have an excellent high voltage withstandability under theabove-described situation, due to the effect of electric fieldrelaxation by the RESURF structure.

Further, in the MOSFET 1 according to the present embodiment, the drainregion 7 is formed at almost the center of the epitaxial region 3. Forexample, assume that the drain region is formed near the isolationregion likewise a conventional MOSFET. In this case, the strength of anelectric field between the drain region and the isolation region israised due to that the voltage level of the drain voltage changes to ahigher level, and a punch through or an undesirable breakdown might becaused. However, in the MOSFET 1, since the drain region 7 is apart fromthe isolation region 4, the strength of an electric field between thedrain region 7 and the isolation region 4 is not raised unlike theconventional MOSFET, even if the voltage level of the drain voltagechanges to a higher level. Therefore, a punch through or an undesirablebreakdown is not easily caused.

As explained above, according to the present invention, it is possibleto provide a semiconductor element having an excellent high voltagewithstandability. Further, according to the present invention, it ispossible to provide a semiconductor element in which a punch through oran undesirable breakdown is not easily caused, and a manufacturingmethod thereof.

The present invention is not limited to the above-described embodiment.For example, in the above-described embodiment, explanation has beenmade by employing as an example a case where each semiconductor regionhas an annular shape when seen from above the MOSFET 1. However, thepresent invention is not limited to this, but each semiconductor regionmay have a rectangular shape when seen from above the MOSFET 1.

Further, in the above-described embodiment, the epitaxial region 3 isformed by an epitaxial growth method. However, it may be formed by alamination technique or the like.

Furthermore, the semiconductor element according to the above-describedembodiment is not limited to a p-channel MOSFET, but may be an n-channelMOSFET. Further, in the above-described embodiment, explanation has beenmade by employing a case where the p-channel MOSFET 1 is formed by usingthe p-type semiconductor substrate 2. However, the present invention isnot limited to this, but a reverse conductive type MOSFET may be formedby using an n-type semiconductor substrate.

This application is based on Japanese Patent Application No. 2002-123615filed on Apr. 25, 2002, and the specification, claims, and drawingsthereof are incorporated wherein in its entirety.

INDUSTRIAL APPLICABILITY

The present invention can be applied to a semiconductor element having aso-called RESURF structure and a manufacturing method thereof.

1. A semiconductor element comprising: a first semiconductor region (2)of a first conductive type; a second semiconductor region (3) of asecond conductive type which is formed on said first semiconductorregion (2); a third semiconductor region (6) of a first conductive typewhich is formed in a predetermined surface area of said secondsemiconductor region (3); a fourth semiconductor region (7) of a firstconductive type which is formed in a surface area of said thirdsemiconductor region (6) and has a higher impurity concentration thansaid third semiconductor region (6) has; and a fifth semiconductorregion (8) formed in a surface area of said second semiconductor region(3) so as to surround said third semiconductor region (6); said thirdsemiconductor region (6) having a central portion (6 a) surrounding saidfourth semiconductor region, and a peripheral portion (6 b) surroundingsaid central portion (6 a); said central portion (6 a) being formed tohave a depth from a surface of said second semiconductor region (3)deeper than that of said peripheral portion (6 b); said secondsemiconductor region (3) arranged right under said central portion (6 a)having a smaller amount of electric charges than an amount of electriccharges of said second semiconductor region (3) arranged generally undersaid peripheral portion (6 b), and said second semiconductor region (3)arranged generally under said central portion (6 a) having a thicknessthinner than that of said second semiconductor region (3) arrangedgenerally under said peripheral portion (6 b); and an isolation region(4) of a first conductive type which is formed at an outer edge of saidsecond semiconductor region (3); and a sixth semiconductor region (5)formed in a surface area of said second semiconductor region (3) so asto contact said isolation region (4), wherein said second semiconductorregion (3) which is present generally under said sixth semiconductorregion (5) has a same thickness as that of said second semiconductorregion (3) which is present generally under said peripheral portion (6b).
 2. A semiconductor element comprising: a first semiconductor region(2) of a first conductive type; a second semiconductor region (3) of asecond conductive type which is formed on said first semiconductorregion (2); a third semiconductor region (6) of a first conductive typewhich is formed in a predetermined surface area of said secondsemiconductor region (3); a fourth semiconductor region (7) of a firstconductive type which is formed in a surface area of said thirdsemiconductor region (6) and has a higher impurity concentration thansaid third semiconductor region (6) has; and a fifth semiconductorregion (8) formed in a surface area of said second semiconductor region(3) so as to surround said third semiconductor region (6); said thirdsemiconductor region (6) having a central portion (6 a) surrounding saidfourth semiconductor region, and a peripheral portion (6 b) surroundingsaid central portion (6 a); said central portion (6 a) being formed tohave a depth from a surface of said second semiconductor region (3)deeper than that of said peripheral portion (6 b); said secondsemiconductor region (3) arranged right under said central portion (6 a)having a smaller amount of electric charges than an amount of electriccharges of said second semiconductor region (3) arranged generally undersaid peripheral portion (6 b), and said second semiconductor region (3)arranged generally under said central portion (6 a) having a thicknessthinner than that of said second semiconductor region (3) arrangedgenerally under said peripheral portion (6 b); and said thirdsemiconductor region (6) is formed at generally a center of a surface ofsaid second semiconductor region (3), and said fourth semiconductorregion (7) is formed at generally a center of a surface of said thirdsemiconductor region (6).
 3. A semiconductor element comprising: a firstsemiconductor region (2) of a first conductive type; a secondsemiconductor region (3) of a second conductive type which is formed onsaid first semiconductor region (2); a third semiconductor region (6) ofa first conductive type which is formed in a predetermined surface areaof said second semiconductor region (3); a fourth semiconductor region(7) of a first conductive type which is formed in a surface area of saidthird semiconductor region (6) and has a higher impurity concentrationthan said third semiconductor region (6) has; and a fifth semiconductorregion (8) formed in a surface area of said second semiconductor region(3) so as to surround said third semiconductor region (6); said thirdsemiconductor region (6) having a central portion (6 a) surrounding saidfourth semiconductor region, and a peripheral portion (6 b) surroundingsaid central portion (6 a); said central portion (6 a) being formed tohave a depth from a surface of said second semiconductor region (3)deeper than that of said peripheral portion (6 b); said secondsemiconductor region (3) arranged right under said central portion (6 a)having a smaller amount of electric charges than an amount of electriccharges of said second semiconductor region (3) arranged generally undersaid peripheral portion (6 b), and said second semiconductor region (3)arranged generally under said central portion (6 a) having a thicknessthinner than that of said second semiconductor region (3) arrangedgenerally under said peripheral portion (6 b); and a ground electrode(15) which is formed on said isolation region (4), wherein said secondsemiconductor region (3) and said third semiconductor region (6) aresubstantially depleted when a voltage of a predetermined level isapplied to between said gate electrode (11) and said drain electrode(12) and said ground electrode (15) is grounded.
 4. A semiconductorelement comprising: a first semiconductor region (2) of a firstconductive type; a second semiconductor region (3) of a secondconductive type which is formed on said first semiconductor region (2);a third semiconductor region (6) of a first conductive type which isformed in a predetermined surface area of said second semiconductorregion (3); a fourth semiconductor region (7) of a first conductive typewhich is formed in a surface area of said third semiconductor region (6)and has a higher impurity concentration than said third semiconductorregion (6) has; and a fifth semiconductor region (8) formed in a surfacearea of said second semiconductor region (3) so as to surround saidthird semiconductor region (6); said third semiconductor region (6)having a central portion (6 a) surrounding said fourth semiconductorregion, and a peripheral portion (6 b) surrounding said central portion(6 a); said central portion (6 a) being formed to have a depth from asurface of said second semiconductor region (3) deeper than that of saidperipheral portion (6 b); said second semiconductor region (3) arrangedright under said central portion (6 a) having a smaller amount ofelectric charges than an amount of electric charges of said secondsemiconductor region (3) arranged generally under said peripheralportion (6 b), and said second semiconductor region (3) arrangedgenerally under said central portion (6 a) having a thickness thinnerthan that of said second semiconductor region (3) arranged generallyunder said peripheral portion (6 b); and said second semiconductorregion (3) generally under a central portion (6 a) has such an amount ofelectric charges as to maintain an electric charge balance near saidfourth semiconductor region (7) in a case where a voltage level of avoltage applied to said fourth semiconductor region (7) is at groundlevel; and said second semiconductor region (3) generally under saidperipheral portion (6 b) has such an amount of electric charges as tomaintain an electric charge balance near said fourth semiconductorregion (7) in a case where a voltage level of a voltage applied to saidfourth semiconductor region (7) is a high level in a plus direction withrespect to the ground level.
 5. A manufacturing method of asemiconductor element comprising: a step of forming a secondsemiconductor region (3) of a second conductive type on a semiconductorsubstrate (2) which constitutes a first semiconductor region of a firstconductive type; a step of forming in a surface area of said secondsemiconductor region (3), a third semiconductor region (6) of a firstconductive type which includes a central portion (6 a) and a peripheralportion (6 b) having different depths from each other, wherein saidcentral portion (6 a) is formed in a predetermined surface area of saidsecond semiconductor region (3), and said peripheral portion (6 b) isformed in a surface area of said second semiconductor region (3) so asto abut on said central portion (6 a) and surround said central portion(6 a) and to have a depth shallower than the depth of said centralportion (6 a); a step of forming a fourth semiconductor region (7) of afirst conductive type having a higher impurity concentration than saidthird semiconductor region (6) has, in a surface region of said centralportion (6 a) included in said third semiconductor region (6); andforming an isolation region (4) of said first conductive type formed atan outer edge of said second semiconductor region (3); and a sixthsemiconductor region (5) formed in said surface area of said secondsemiconductor region (3) so as to contact said isolation region (4),wherein said second semiconductor region (3) is present generally undersaid sixth semiconductor region (5) has a similar thickness as that ofsaid second semiconductor region (3) which is present generally undersaid peripheral portion (6 b).